1. Field of the Invention
This invention relates to a timing recovery circuit, and more particularly, to a phase lock loop circuit for recovering the timing from sparse timing information in multi-level or partial response codes.
2. Description of Related Art
Digital data transmission has become increasingly important and accordingly, the need to provide more reliable digital data transmission continues to propel the search for superior systems for recovering timing from a received line code. In order to utilize the bandwidth of the channel effectively, many digital transmission systems have begun to use band efficient multi-level line codes, such as 2B1Q (two-bit coded into one quat symbol) and partial response codes. Although multi-level line codes improve system performance, these line codes make the timing recovery and the pulse shaping more difficult because of the non-self timed characteristics of the line code itself.
The prior art traditionally used analog signal processing of the incoming data signal to derive a timing signal. However, most digital receivers use digital processing techniques to recover the digital information which is modulated on the incoming pulse train. Consequently, the received signal is sampled at discrete time intervals and converted to digital amplitude magnitudes. Any additional processing is accomplished using digital circuitry. To minimize cost and complexity, the incoming signal is usually sampled at the lowest possible rate, i.e., the baud rate. However, sampling at the baud rate creates aliasing distortion when the analog signal waveform is reconstructed. Therefore, analog timing recovery techniques cannot generally be used in digital receivers which operate at the baud rate.
One prior art technique for overcoming this problem is taught by Kurt H. Mueller and Markus Muller in an article entitled "Timing Recovery in Digital Synchronous Data Receivers," IEEE TRANSACTIONS ON COMMUNICATIONS, Volume COM-20, May 1976, pages 516-530, herein incorporated by reference. In this article, a preselected timing function is used to describe the optimal sampling instant. The coefficient values of this timing function are then estimated from the arriving signal samples. However, since timing jitter depends on the actual pulse sequence transmitted as well as the impulse response, the timing function estimates have a relatively high variance. Further, if the channel response is heavily distorted by the bridged taps, this technique cannot be used.
U.S. Pat. No. 5,020,078 to Crespo issued May 28, 1991, herein incorporated by reference, provides a technique for recovering the transmitted signal from the received signal by using a decision feedback equalizer to estimate and then remove the intersymbol interference. A second decision feedback equalizer is used to estimate the timing of the sampling pulse. An optimum timing phase is derived by driving the sampling clock with a phase adjustment signal optimizing the amplitude of the sampling pulse. However, the decision feedback equalizer may be subjected to precursor intersymbol interference which cannot be cancelled.
There is a need, therefore, for a simple device for recovering timing from multi-level codes transmitted over heavily distorted channels.